This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Generally, back-gating is a particular device feature in fully depleted silicon on insulator (FD-SOI) over Fin-Fet technology that allows adjusting the threshold voltage for the front-gate. Standard chip architecture places voltage regulation on a high-side to thereby generate VDD for some core power domains with a common low-side VSS=GND. Certain FD-SOI technologies define VSS as the common reference potential for the back-gates of N- and P-MOS. To use back-gating, biasing potentials need to be generated and the associated power consumption has to be considered. As a consequence, reverse body-biasing of NMOS devices or forward body-biasing of PMOS devices require the generation of negative voltages, typically by charge pumping. This can have multiple drawbacks including, in one example, charge pumps are clocked circuits and cause considerable power and chip-area overhead, while modifications lowering their power consumption typically degrade the quality of the supplies generated (increased ripple).
Further, in bulk CMOS designs, the threshold voltage increases as the supply voltage reduces due to drain-induced barrier lowering (DIBL). This can be detrimental to circuit performance; however, the drive-strength ratio between P-N can be approximately maintained by trading off the differences in DIBL against the set-point of the threshold voltages at nominal (VDD-VSS). While DIBL is detrimental to performance, maintaining the drive-strength ratio is important to guarantee the operation of logic circuits over a large range of supply voltages (VDD-VSS). By contrast, FD-SOI technologies show reduced DIBL, yet using VSS as common reference potential for the back-gate exposes only the PMOS to a change in the back-gate potential as the supply voltage VDD is varied. Consequently such FD-SOI technologies do not preserve the ratio of between P-N drive-strength over a large range of supply voltages, compromising the function of logic circuits. As such, there exists a need to improve the configuration for voltage regulation in FD-SOI technology using VSS as a common reference for the back-gate of N- and P-MOS so as to improve the ability of circuits to operate over an extended range of supply voltages with low power consumption.